“Conductive bridging” memory cells (CBRAM) constitute a new and promising technology for semiconductor-based memory components. In the future, products based on CB technology are possible as a replacement both for flash memories and for DRAM memories. R. Symanczyk et al. describe in “Electrical characterization of solid state ionic memory elements” in Non-Volatile Memory Technology Symposium (NVMTS'03), San Diego, 2003, the electrical properties of memory elements based on so-called solid electrolytes, these elements also being called programmable metallization cells, or PMC when abbreviated, on account of their operating principle. In memory cells of this type, a vitreous or porous layer, for example made of chalcogenide glass such as GeSe, GeS or made of AgSe, CuS, WOx, etc., is situated between a metal electrode serving as ion donor, for example made of Cu, Ag, Au, Zn, and a counterelectrode made of inert material, for example W, Ti, Ta, TiN, doped Si or Pt. When a voltage or current pulse is applied between the electrodes, metal ions are driven into the chalcogenide glass by a redox reaction and form metal-enriched clusters, with the result that, given a sufficient metal concentration, a conductive bridge is formed between the two electrodes, which forms a low-resistance or “on” state of the memory cell. An electrical current or voltage pulse having opposite polarity inverts the redox reaction, so that the metal ions are drawn from the chalcogenide glass and the metal-enriched clusters are reduced. In this way, the metallically conductive bridge is terminated, and a high-resistance or “off” state of the memory cell then forms.
The accompanying FIGS. 1A and 1B schematically illustrate the above mentioned possible states of such a CBRAM memory cell 1, namely the high-resistance or off state in FIG. 1A and the low-resistance or on state in FIG. 1B, it being possible for the high-resistance state to be assigned for example to the logic state “0” and the low-resistance state to the logic “1” state. FIGS. 2A and 2B schematically illustrate a write operation for writing a logic “1” by application of a current or voltage pulse to the CBRAM memory cell 1, while FIGS. 2C and 2D schematically illustrate an erase operation in which a CBRAM memory cell 1 in the low-resistance or on state is put into the high-resistance or off state (FIG. 2D) by application of a current or voltage pulse having opposite polarity.
The suitability of such memory cells for high-density and fast nonvolatile memories has been recognized and investigated in the specialist report mentioned above.
For reliable operation over relatively long times, special programming and erasure strategies are necessary in order to guarantee the cycle stability. The accompanying FIG. 3 graphically shows the result of a typical cycle test such as occurs with an inadequately calibrated erase operation: the number of cycles with which the CBRAM cell was cycled is plotted on the abscissa axis and the electrical resistance of the CBRAM cell is plotted on the ordinate axis. Since the on state was written to a greater degree than erased, the resistance of the off state thus generated degrades with an increasing number of cycles. It is thus clear that in the extreme case, direct repeated writing of a logic “1” state corresponding to the on state in CBRAM memory cells causes serious write imprint and the cell would be very rapidly destroyed.